About The Author

For those curious about the influences on the SecureRISC ISAs, prior to starting these explorations, my previous experience was with the following ISAs: following:

* Wrote compiler code generators
† Wrote operating systems for
‡ Designed ISA

I was actually the designer of the S-2, the MIPS 64‑bit extension, and Xtensa ISAs. The S-2 was a pre-RISC ISA circa the early 1980s, somewhat RISC-like, but with one memory operand in every instruction (somewhat similar to the PDP-10). It was a reaction to the S-1 which was many boards of logic, whereas the S-2 was meant to fit onto just two boards of logic (this gave its RISC-like character). I became Director of Architecture at MIPS after the 32‑bit ISA was defined, and defined the 64‑bit extension circa the late 1980s, but I disagreed with many design choices in the original MIPS ISA, such as the lack of load interlocks branch delay slots, absolute addresses in JAL, and so on. While I was the principal architect of the Xtensa ISA in the late 1990s, corporate priorities (e.g. embedded focus and code size) were such that many design choices were not to my liking (e.g. the 24‑bit instruction width). Thus the SecureRISC family of ISAs are the first contemporary deisgns where the choices are really my own.

In addition, I had some knowledge of the following ISAs:

Surprisingly, I am not very familiar with the ARM instruction set.

My operating system experience and influences included the following:

* Contributed kernel code

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SecureRISC/AboutAuthor.html 2023-01-08